An Architecture for FPGA realisation of a fast chaotic block cipher for image encryption byM, Udaykiran ; Supervised bySamrat L. Sabat
Udaykiran,M| Call Number | PR621.381 U1A |
| Author | Udaykiran,M |
| Title | An Architecture for FPGA realisation of a fast chaotic block cipher for image encryption byM, Udaykiran ; Supervised bySamrat L. Sabat |
| Publication | Hyderabad: University of Hyderabad, 2016. |
| Physical Description | 59p. |
| Notes | Master of Technology - Centre for Advanced Studies in Electronics Science and Technology - School of Physics - University of Hyderabad |
| Added Author | Sabat, Samrat L.; Supervisor |
| Subject | INTEGRATED CIRCUIT TECHNOLOGY - PROJECT |
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$a An Architecture for FPGA realisation of a fast chaotic block cipher for image encryption $c byM, Udaykiran ; Supervised bySamrat L. Sabat
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$a Master of Technology - Centre for Advanced Studies in Electronics Science and Technology - School of Physics - University of Hyderabad
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| Notes | Master of Technology - Centre for Advanced Studies in Electronics Science and Technology - School of Physics - University of Hyderabad |
| Subject | INTEGRATED CIRCUIT TECHNOLOGY - PROJECT |