VLSI architechture of system on chip (SOC) for image compression by Pulipati John Paul; supervised by P.N. Girija
John Paul, Pulipati| Call Number | TH001.6 J61V |
| Author | John Paul, Pulipati |
| Title | VLSI architechture of system on chip (SOC) for image compression by Pulipati John Paul; supervised by P.N. Girija |
| Publication | Hyderabad: University of Hyderabad , 2007. |
| Physical Description | 95p. |
| Notes | Thesis (Ph.D) - Philosophy - Department of Compuer and Information Sciences - School of Mathematics, Computer and Information Sciences, University of Hyderabad. |
| Added Author | Girija, P.N.; supervisor |
| Subject | COMPUTER SCIENCE - THESIS |
| Multimedia |
Total Ratings:
0
01003nam a2200217 a 4500
001
vtls001493516
003
VRT
005
20210409152000.0
008
120904s m 00000 eng d
039
9
$a 202104091520 $b brrao $c 201811131300 $d thirupathi $c 201811131237 $d thirupathi $c 201209041834 $d VLOAD $y 200907011436 $z 696yak
082
$a TH001.6 $b J61V
100
1
$a John Paul, Pulipati
245
1
0
$a VLSI architechture of system on chip (SOC) for image compression $c by Pulipati John Paul; supervised by P.N. Girija
260
$a Hyderabad: $b University of Hyderabad , $c 2007.
300
$a 95p.
500
$a Thesis (Ph.D) - Philosophy - Department of Compuer and Information Sciences - School of Mathematics, Computer and Information Sciences, University of Hyderabad.
650
0
$a COMPUTER SCIENCE - THESIS
700
$a Girija, P.N.; supervisor
856
4
$u http://igmlnet.uohyd.ac.in:8000/hi-res/hcu_images/TH4833.pdf
999
$a VIRTUA40
999
$a VTLSSORT0080*0820*1000*2450*2600*3000*5000*6500*7000*8560*9992
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| Notes | Thesis (Ph.D) - Philosophy - Department of Compuer and Information Sciences - School of Mathematics, Computer and Information Sciences, University of Hyderabad. |
| Subject | COMPUTER SCIENCE - THESIS |
| Multimedia |