Leakage in nanometer CMOS technologies / [ed. by] Siva G. Narendra, Anantha Chandrakasan.
Narendra,Siva G.| Call Number | 620.5 N16L |
| Author | Narendra,Siva G. |
| Title | Leakage in nanometer CMOS technologies / [ed. by] Siva G. Narendra, Anantha Chandrakasan. |
| Publication | New York : Springer, 2006. |
| Physical Description | x, 307 p. : ill. ; 24 cm. |
| Series | Series on integrated circuits and systems |
| Contents | Taxonomy of leakage : sources, impact, and solutions - Leakage dependence on input vector / Power gating and dynamic voltage scaling / Methodologies for power gating / Body biasing / Process variation and adaptive design / Memory leakage reduction / Active leakage reduction and multi-performance devices / Impact of leakage power and variation on testing / Case study : leakage reduction in Hitachi/Renesas microprocessors / Case study : leakage reduction in the Intel Xscale microprocessor / |
| Added Author | Narendra, Siva G. 1971- Chandrakasan, Anantha P. |
| Subject | Metal oxide semiconductors, Complementary Design and construction. Integrated circuits Design and construction. Electric leakage Prevention. |
| Multimedia |
Total Ratings:
0
02673nam a2200433Ia 4500
001
vtls001455511
003
VRT
005
20060811110700.0
008
051208s2006 nyua b 001 0 eng d
010
$a 2005-932184
015
$a GBA611887 $2 bnb
016
7
$a 013370123 $2 Uk
020
$a 0387257373
020
$a 0387281339 (e-book)
024
3
$a 9780387257372
024
3
$a 9780387281339
029
1
$a OHX $b har055020027
039
9
$a 200608111107 $b 361 $c 200605061533 $d srinu $y 200605061533 $z srinu
040
$a RCE $c RCE $d BAKER $d UKM $d OHX $d DLC
049
$a IIUOH
082
0
4
$a 620.5 $b N16L
100
$a Narendra,Siva G.
245
0
0
$a Leakage in nanometer CMOS technologies / $c [ed. by] Siva G. Narendra, Anantha Chandrakasan.
260
$a New York : $b Springer, $c 2006.
300
$a x, 307 p. : $b ill. ; $c 24 cm.
440
0
$a Series on integrated circuits and systems
504
$a Includes bibliographical references and index.
505
0
0
$t Taxonomy of leakage : sources, impact, and solutions - $t Leakage dependence on input vector / $r Siva Narendra ... [et al.] - $t Power gating and dynamic voltage scaling / $r Benton Calhoun, James Kao, and Anantha Chandrakasan - $t Methodologies for power gating / $r Kimiyoshi Usami and Takayasu Sakurai - $t Body biasing / $r Tadahiro Kuroda and Takayasu Sakurai - $t Process variation and adaptive design / $r Siva Narendra ... [et al.] - $t Memory leakage reduction / $r Takayuki Kawahara and Kiyoo Itoh - $t Active leakage reduction and multi-performance devices / $r Siva Narendra ... [et al.] - $t Impact of leakage power and variation on testing / $r Ali Keshavarzi and Kaushik Roy - $t Case study : leakage reduction in Hitachi/Renesas microprocessors / $r Masayuki Miyazaki, Hiroyuki Mizuno, and Takayuki Kawahara - $t Case study : leakage reduction in the Intel Xscale microprocessor / $r Lawrence Clark - Transistor design to reduce leakage / $r Sagar Suthram, Siva Narendra, and Scott Thompson.
650
0
$a Metal oxide semiconductors, Complementary $x Design and construction.
650
0
$a Integrated circuits $x Design and construction.
650
0
$a Electric leakage $x Prevention.
700
1
$a Narendra, Siva G. $q (Siva Gurusami), $d 1971-
700
1
$a Chandrakasan, Anantha P.
856
4
1
$3 Table of contents $u http://www.loc.gov/catdir/toc/fy0607/2005932184.html
938
$a Otto Harrassowitz $b HARR $n har055020027 $c 88.76 EUR
938
$a Baker & Taylor $b BKTY $c 99.00 $d 99.00 $i 0387257373 $n 0006485022 $s active
994
$a C0 $b IIUOH
999
$a VIRTUA
999
$a VTLSSORT0010*0030*0080*0100*0400*0150*0160*0200*0201*0240*0241*0290*0820*0490*1000*2450*2600*3000*4400*5040*5050*6500*6501*6502*7000*7001*8560*9380*9381*9940*9991
No Reviews to Display
| Contents | Taxonomy of leakage : sources, impact, and solutions - Leakage dependence on input vector / Power gating and dynamic voltage scaling / Methodologies for power gating / Body biasing / Process variation and adaptive design / Memory leakage reduction / Active leakage reduction and multi-performance devices / Impact of leakage power and variation on testing / Case study : leakage reduction in Hitachi/Renesas microprocessors / Case study : leakage reduction in the Intel Xscale microprocessor / |
| Subject | Metal oxide semiconductors, Complementary Design and construction. Integrated circuits Design and construction. Electric leakage Prevention. |
| Multimedia |