Design and Implementation of Matrix Algebra Accelerators on FPGA for Signal Processing Applications using High-Level Synthesis : by K. Venkata Siva Kumar ; supervised by Samrat L. Sabat
Venkata Siva Kumar, K.| Call Number | TH621.381 |
| Author | Venkata Siva Kumar, K. |
| Title | Design and Implementation of Matrix Algebra Accelerators on
FPGA for Signal Processing Applications using High-Level Synthesis : by K. Venkata Siva Kumar ; supervised by Samrat L. Sabat |
| Publication | Hyderabad: University of Hyderabad, 2025. |
| Physical Description | 144 p. |
| Notes | E-Copy |
| Added Author | Samrat L. Sabat supervisor |
| Subject | ELECTRONICS SCIENCE - THESES Matrix Algebra Accelerators High-Level Synthesis FPGA for Signal Processing |
| Multimedia |
Total Ratings:
0
01216nam a2200265 a 4500
001
vtls001609109
003
VRT
005
20260317110100.0
008
260317 m 000 0 eng d
039
9
$y 202603171101 $z hanu
082
$a TH621.381
100
1
$a Venkata Siva Kumar, K.
245
1
$a Design and Implementation of Matrix Algebra Accelerators on
FPGA for Signal Processing Applications using High-Level Synthesis : $c by K. Venkata Siva Kumar ; supervised by Samrat L. Sabat
260
$a Hyderabad: $b University of Hyderabad, $c 2025.
300
$a 144 p.
500
$a E-Copy
502
$a Theses (Ph.D) - Center for Advanced Studies in Electronics Science and Technology Center for Advanced Studies in Electronics Science and Technology (CASEST) - School of Physics - University of Hyderabad - Hyderabad - 500046.
650
0
$a ELECTRONICS SCIENCE - THESES
650
$a Matrix Algebra Accelerators
650
$a High-Level Synthesis
650
$a FPGA for Signal Processing
700
1
$a Samrat L. Sabat $e supervisor
856
4
$u http://igmlnet.uohyd.ac.in:8000/hi-res/hcu_images/TH13608.pdf
999
$a VIRTUA40
999
$a VTLSSORT0080*0820*1000*2450*2600*3000*5000*5020*6500*6501*6502*6503*7000*8560*9992
No Reviews to Display
| Notes | E-Copy |
| Subject | ELECTRONICS SCIENCE - THESES Matrix Algebra Accelerators High-Level Synthesis FPGA for Signal Processing |
| Multimedia |