Reconfigurable architectures and algorithms: A research survey

Abstract

Ever since the introduction of the Dynamically Reconfigurable Buses, the architecture gained a lot of popularity amongst the researchers and scientists for its high performance computing with general purpose processor used. It is a powerful model of computation in which communication pattern between the processors could be changed during the execution. Following the years several new architectures and efficient algorithms for these were proposed, and their implementation using FPGA's have been shown. This paper presents a survey on the different architectures proposed, and few important algorithms presented for these specialized architectures over the period of last two decades. © 2009 Technomathematics Research Foundation.