Development of FPGA based coprocessors for signal processing applications

Abstract

Now-a-days there has been an increase in demand for designing recon- gurable embedded systems in signal processing, multimedia and evolutionary computation applications. Embedded processors alone, cannot achieve the desired computational capability to ful ll the requirements of massive parallelism, higher memory bandwidth, higher execution speed to execute these applications. In order to meet these requirements, Field Programmable Gate Arrays (FPGAs) are used by exploiting the recon gurable resources. Beyond their well-known exibility, FPGAs o er the versatility of running software applications on embedded processors and at the same time taking the advantage of available recon gurable resources, all on same package. FPGA based System on Chip (SoC) design solution replaces traditional System on Board (SoB) design concept and is often referred as Programmable SoC (PSoC). This platform consists of hard/soft embedded processors, external memory and custom Intellectual Properties (IPs). These IPs are used to accelerate the computational task of an algorithm. This involves developing dedicated IP and its integration in SoC platform. There are mainly two types of IP interfacing techniques, i.e., Slave Unit (SU) and Auxiliary Processing Unit (APU). The SU interface has Register/First-In-First-Out (FIFO) connected to the processor through shared system bus (Processor Local Bus (PLB)). Although this interface is simpler in design, the main bottleneck is bus arbitration, which lowers the total execution speed. The other bus interface is APU (only for PowerPC440), which can be directly connected to the custom IP through a dedicated Fabric coprocessor Bus (FCB). This interface has no communication overhead and allows quick synchronization between the processor and IP. Custom IPs have been developed and integrated using APU interface for maximizing the portability and modularity.