Centre for Modelling, Simulation and Design

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Browsing Centre for Modelling, Simulation and Design by Author "Anurag,"
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    A novel scheme for Compiler Optimization Framework
    ( 2015-09-24) Chebolu, N. A.B.Sankar ; Anurag, ; Wankar, Rajeev
    Determining nearly optimal optimization options and selecting the right values for compiler parameter set is a combinatorial problem. In order to obtain the maximal performance, sophisticated tuning strategies were employed by many researchers. Enormous tuning times are the main hindrance for the application of these strategies in production compilers. Also the existing compiler optimization frameworks do not completely capture the requirements of modern day systems and their performance objectives. In order to mitigate the problem of enormous tuning times and also to capture the requirements of the modern day systems, we are proposing a novel scheme for Compiler Optimization Framework, called Compiler Optimization Adaption Scheme. As part of this scheme, we propose the Objective-specific Tuned Libraries, which will be used to link with the applications as per the desired performance objective. Details of the experimentation supporting our ideas behind the scheme including Objective-specific Tuned Libraries are also presented.
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    On prediction accuracy of machine learning algorithms for characterizing shared L2 cache behavior of programs on multicore processors
    ( 2009-11-05) Rai, Jitendra Kumar ; Negi, Atul ; Wankar, Rajeev ; Nayak, K. D. ; Anurag,
    Information on a particular behavioral aspect of a program can be useful to know about the performance bottlenecks and can be utilized further to improve the performance of the system. It is observed that contention for shared L2 cache between programs running on a Multi-Core Processor (MCP) is one of the performance bottlenecks. The utilization of the L2 cache by a program, while sharing it with others on a MCP is a metric of interest to frame policies that reduce contention. In this work we investigate the ability of some of the machine learning algorithms to predict the solo run L2 cache stress of a running program on Intel quad-core Xeon X5482 processor. Data collected from hardware performance counters of Intel quad-core Xeon X5482 processor were utilized to derive the attributes to train the machine learning algorithms. We observed that the best performing machine learning algorithm in this context is Model tree (M5'), followed by Artificial Neural Networks (ANN). © 2009 IEEE.